Semiconductor devices are subjected to a series of test procedures in order to confirm functionality and yield, and to assure quality and reliability. This testing procedure conventionally includes "probe testing", in which individual dice, while still on a wafer, are initially tested to determine functionality and speed. Probe cards are used to electrically test die at that level. The electrical connection interfaces with only a single die at a time in wafer, before the dice are singulated from wafer.
If the wafer has a yield of functional dice which indicates that quality of the functional dice is likely to be good, each individual die is traditionally assembled in a package to form a semiconductor device. Conventionally, the packaging includes a lead frame and a plastic or ceramic housing.
The packaged devices are then subjected to another series of tests, which include burn-in and discrete testing. Discrete testing permits the devices to be tested for speed and for errors which may occur after assembly and after burn-in. Burn-in accelerates failure mechanisms by electrically exercising the devices (devices under test or DUT) at elevated temperatures, elevated dynamic biasing schemes. This induces infant mortality failure mechanisms and elicit potential failures which would not otherwise be apparent at nominal test conditions.
Variations on these procedures permit devices assembled onto circuit arrangements, such as memory boards, to be burned-in, along with the memory board in order to assure reliability of the circuit board and the circuit board assembly and manufacturing process, as populated with devices. This closed assembly testing assumes that the devices are discretely packaged in order that it can then be performed more readily.
Semiconductor packaging has been referred to in terms of "levels" of packaging. The chip capsule generally constitutes a first level of packaging. A second level would then be a "card" or a printed circuit board. A third level may include second level packaging combined with a motherboard. A fourth level may follow the third level. In each case, the packaging to any level involves cost.
It is proposed that devices be packaged without conventional lead frames. This creates two problems for conventional test methods. Firstly, discrete testing is more difficult because the conventional lead frame package is not used. Furthermore, multiple device may be assembled into a single package, thereby reducing the performance of the package to that of the die with the lowest performance. This is because the ability to presort the individual dice is limited to that obtained through probe testing. Secondly, the packaging may have other limitations package assembly defect mechanisms which are aggravated by burn-in stress conditions so that the packaging becomes a limitation for burn-in testing.
According to the invention represented by U.S. Pat. No. 4,899,107, to Alan Wood and Tim Corbett, a reusable burn-in/test fixture for discrete die is provided. The fixture consists of two halves, one of which is a die cavity plate for receiving semiconductor dice as the devices under test (DUT); and the other half establishes electrical contact with the dice and with a burn-in oven.
The first half of the test fixture contains cavities in which die are inserted circuit side up. The die will rest on a floating platform. A support mechanism under the die platform will provide a constant uniform pressure or force to maintain adequate electrical contact to the die contacts on the DUT to probe tips on the second half. The support mechanism will compensate for variations of overall die thickness.
The second half has a rigid high temperature rated substrate, on which are mounted probes for each corresponding die pad. Each probe is connected to an electrical trace on the substrate (similar to a P.C. board) so that each die pad of each die is electrically isolated from one another for high speed functional testing purposes. The probe tips are planar so that contact to each die pad occurs simultaneously. The probe tips are arranged in an array to accommodate eight or more dice. The traces from the probes terminate in edge fingers to accept a conventional card edge connector. The geometry of the probes and edge fingers are optimized to avoid electrical test artifacts.
The two halves of the test fixture are joined so that each pad on each die aligns with a corresponding electrical contact. The test fixture is configured to house groups of 8 or 16 die for maximum through put efficiency of the functional testers. The test fixture need not be opened until the burn-in and electrical test are completed. After burn-in stress and electrical test, the die are removed from the test fixture and depositioned accordingly. The fully burned-in and tested die are available for any type of subsequent assembly applications.
That technique allows all elements of the burn-in/test fixture to become fully reusable, while permitting testing of individual dice in a manner similar to that accomplished with discrete packaged semiconductor devices.
An ability to extend accelerated burn-in and functional/parametric/speed testing of dice to include accelerated burn-in and functional, parametric and speed testing while the dice are still on the wafer would have several advantages. Since each step in the assembly and package process represents commitment of resources, early determination of defective parts or ability to predict a failure at a conventional burn-in stage is advantageous. It would be further advantageous to be able to predict a failure at a burn-in stage prior to assembly. Clearly, if a part can be made to fail prior to assembly, assembly resources can be directed to a higher percentage of good parts.
There exists a significant market for uncut fabricated wafers. These wafers are referred to as "probe wafers" because they are delivered after probe testing, which follows fabrication. The purchase of probe wafers is primarily by "ASIC assembly houses" which custom package parts, including parts traditionally considered to be "commodity" chips. The purchase of uncut wafers is usually based on the recent yield rate of the semiconductor manufacturer, but recent yields are not a strong indicator of the yield of any given wafer lot. Furthermore, the assembly process techniques used by the assembly house have a significant effect on yield.
Characterization, such as speed grading is even more variable than yield. While a packaged DRAM is purchased by the consumer based on the part's speed grade, speed grading of probe wafers is almost a matter of conjecture. That means that it is happenchance as to whether the assembly house purchases a wafer of mostly "-10" parts (100 ns) or mostly "6" parts (60 ns).
Recent developments in fabrication technology have resulted in such speed characterizations being more uniform on any given wafer. This has made it possible to provide wafers in which a majority of good dice have speed grades which do not greatly exceed an average for the wafer. Such uniformity, along with an ability to achieve fuse repairs and patches, have made wafer scale integration of arrays and cluster packaging practical.
Other developments include an ability to track individual dice on wafers, starting at probe. Traditionally, probe identifies bad dice, (example, an ink spot.) The assembly process is continued only for dice which do not have the ink spots. By computer tracking, the ink spot becomes superfluous, as a map of good and bad dice are stored and transferred to subsequent assembly steps.
Although the dice are singulated, there are cases in which the discrete parts are reassembled into an array after assembly. An example is in computer memory, in which one or more banks of memory are composed of arrays of memory chips. It would be advantageous to be able to select good dice on a wafer and assemble the dice into an array without singulating the dice. This would allow a much denser array of good clustered dice on a single piece of silicon.
It is an object of the invention to increase handling efficiency, while at the same time reducing the required size of the test fixture.